verilog - Systemverilog code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class -

verilog - Systemverilog code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class -

i see compile error:

// near " gmii_interface": syntax error, unexpected identifier, expecting class"//

in model sim when compile next testcase.sv code:

`include "d:/users/rajesh/gmii/interface.sv" `include "d:/users/rajesh/gmii/environment.sv" programme testcase(gmiiinterface tx_intf); environment env; initial begin $display("\n########################################################"); $display("############# start verification ##################"); env = new(tx_intf); env.build(); env.reset(); env.start(); env.waitforend(); env.report(); $display("\############# end verification ###################"); $display("\#########################################################"); end endprogram: testcase

the corresponding interface.sv file code below:

//component name: interface // date: june 14, 2014 interface gmii_interface; logic tx_en; logic tx_er; logic tx_clk; logic [7:0] tx_data; logic rx_en; logic rx_er; logic rx_clk; logic [7:0] rx_data; endinterface : gmii_interface

i'm sv beginner, help appreciated.

gmiiinterface not same gmii_interface.

verilog system-verilog uvm