Array Type is not constrained - VHDL -

Array Type is not constrained - VHDL -

i wrote test bench next vhdl code:

library ieee; utilize ieee.std_logic_1164.all; ---use ieee.std_logic_unsigned.all; utilize ieee.numeric_std.all; entity division3 port(num1, num2 : in std_logic_vector(7 downto 0); quotient : out std_logic_vector(15 downto 0)); end division3; architecture arch_div3 of division3 signal v_test_variable1 : integer; signal v_test_variable2 : integer; begin p3: process(num1, num2) variable n_times: integer:=1; begin if(num1>num2) v_test_variable1 <= to_integer(unsigned(num1)) ; v_test_variable2 <= to_integer(unsigned(num2)) ; l1:loop n_times := n_times + 1; exit when ((v_test_variable2 - v_test_variable1)>0); v_test_variable1 <= v_test_variable1 - v_test_variable2; end loop l1; quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length)); elsif (num2>num1) v_test_variable1 <= to_integer(unsigned(num1)) ; v_test_variable2 <= to_integer(unsigned(num2)) ; l2:loop n_times:=n_times+1; exit when ((v_test_variable1 - v_test_variable2)>0); v_test_variable2 <= v_test_variable2 - v_test_variable1; quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length)); end loop l2; else quotient <= x"0001"; end if; end process p3; end arch_div3;

the testbench:

library ieee; utilize ieee.std_logic_1164.all; --use ieee.std_logic_unsigned.all; utilize ieee.numeric_std.all; -- entity declaration testbench.dont declare ports here entity division3_tb end division3_tb; architecture behavior of division3_tb -- component declaration unit under test (uut) component test --'test' name of module needed tested. --just re-create , paste input , output ports of module such. port(num1, num2 : in std_logic_vector(7 downto 0); quotient : out std_logic_vector(15 downto 0)); end component; --declare inputs , initialize them signal num1 : std_logic_vector := "00000000"; signal num2 : std_logic_vector := "00000000"; --declare outputs , initialize them signal quotient : std_logic_vector(15 downto 0); -- clock period definitions constant clk_period : time := 1 ns; begin -- instantiate unit under test (uut) uut: test port map ( num1 => num1, num2 => num2, quotient => quotient ); -- clock process definitions( clock 50% duty cycle generated here. clk_process :process begin num1 <= "00001000"; wait clk_period/2; --for 0.5 ns signal '0'. num1 <= "00001110"; wait clk_period/2; --for next 0.5 ns signal '1'. end process; -- stimulus process stim_proc: process begin wait 7 ns; num2 <="00000001"; wait 3 ns; num2 <="00000010"; wait 17 ns; num2 <= "00000011"; wait 1 ns; num2 <= "00000110"; wait; end process; end;

on compilation getting error in architecture, saying:

** error: c:/actel/libero_v9.1/model/division3_tb.vhd(19): array type 'num1' not constrained. ** error: c:/actel/libero_v9.1/model/division3_tb.vhd(20): array type 'num2' not constrained. ** error: c:/actel/libero_v9.1/model/division3_tb.vhd(55): vhdl compiler exiting

i bit new vhdl. can explain me constraints on array type? thanks.

the range constrain missing on signal declaration based on std_logic_vector, declaration of num1 , num2 should be:

signal num1 : std_logic_vector(7 downto 0) := "00000000"; signal num2 : std_logic_vector(7 downto 0) := "00000000";

the reason std_logic_vector type declared without range (vhdl-2002):

type std_logic_vector array (natural range <>) of std_logic;

in context legal declare objects without range (called unconstrained), function arguments , entity ports, signals must declared explicit range (called constrained), since signals potentially converted straight wires in design.

btw. may want revisit of additional comments in previous answer, since can see division3 module may still have room improvement.

vhdl