frequency - Vhdl rising_edge statement not synthesizable -

frequency - Vhdl rising_edge statement not synthesizable -

i writing little programme utilize on zybo fpga, supposedly variable frequency divider 10 different steps.

however on lastly line when seek output clock led testing purposes gives me error: line 137: statement not synthesizable since not hold value under not(clock-edge) condition

here code

entity stappenmotor port ( reset, clk : in std_logic; x1, x2 : in std_logic; z1 : out std_logic); end stappenmotor; architecture behavioral of stappenmotor signal speed : integer := 0; signal puls : std_logic; begin speed_proc: process(x1, x2) begin if (rising_edge(x1) , speed < 10) speed <= speed + 1; elsif (rising_edge(x2) , speed > 0) speed <= speed - 1; end if; end process speed_proc; freq_proc: process(clk) variable int : integer := 0; begin if rising_edge(clk) int := int + 1; end if; case speed when 0 => if int = 250000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 1 => if int = 200000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 2 => if int = 175000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 3 => if int = 150000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 4 => if int = 125000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 5 => if int = 100000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 6 => if int = 75000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 7 => if int = 62500000 puls <= '1'; int := 0; else puls <= '0'; end if; when 8 => if int = 50000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 9 => if int = 35000000 puls <= '1'; int := 0; else puls <= '0'; end if; when 10 => if int = 25000000 puls <= '1'; int := 0; else puls <= '0'; end if; when others => if int = 10000000 puls <= '1'; int := 0; else puls <= '0'; end if; end case; end process freq_proc; test: process(puls) begin if rising_edge(puls) z1 <= '1'; else z1 <= '0'; end if; end process test; end behavioral;

error occurs on line:

if rising_edge(puls)

anyone got clue?

kind regards.

all of processes have issues, though compiler may not complain them loudly 1 in test.

in speed_proc, qualifying rising_edge() additional comparison. recommend nesting if statements instead (put comparing if within rising_edge() if). you're trying clock same register 2 separate clocks. need find different way this.

in freq_proc, variable increment within rising_edge() check - don't see reason not set rest in well. it's more standard, , should lead fewer unexpected problems.

in test, @chiggs mentioned, you're trying accomplish invalid. if want toggle z1 every clock cycle, can do:

if rising_edge(puls) z1 <= not z1; end if;

(for simulation, you'd need initialize z1 see valid output.)

vhdl frequency