Creating a time delay in Verilog that can be synthesized -



Creating a time delay in Verilog that can be synthesized -

i attempting create time delay synthesize, , not work in simulation. delay needs 1.439548 ms or close possible precision. using lattice diamond , machx02 7000he fpga. delay used wait specified time required between info transactions. far using internal oscillator run separate counter used spit out info 1 bit @ time @ specified time intervals (using 2.15mhz @ 38400 baud). need utilize clock/counter delay? if so, familiar how define , utilize clock board? confused , lastly requirement program. help appreciated.

used internal oscillator , counter right time delay. counter value determined time required output 40 info bits @ 2.15 mhz frequency.

time delay verilog synthesize lattice-diamond

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