output - Outputting a bitstream onto a pin in verilog -

output - Outputting a bitstream onto a pin in verilog -

i need output 32bit bit-stream onto pin in verilog. know verilog has streaming operators pack , unpack not believe want do.

i have 32x512 fifo ram in info stored. info variable "i" stored on first 32 bits , info variable "q" stored on next 32 bits (the rest of fifo saves info in alternating fashion). need continually 32bit stream off fifo ram , output 32bit info stream onto pin. fifo has 3 output signals(a signal 32 bit info stream(32_data), signal when fifo empty (32_empty), , signal when fifo full(32_full)) sudo code next (it's sudo code because know how else part need help , wanted maintain simple understanding):

process @ posedge clock begin if (32_empty != 1) //if fifo has info if (32_full == 1) //if fifo full, lose info (for testing purposes know if need create ram bigger pin_1 <= 1; //output onto pin fifo total pin_2 <= 0; //clear pin 2 outputting info "i" pin_3 <= 0; //clear pin 3 outputting info "q" else if (en_q == 0) (stream 32bit info variable "i" onto pin 2) //variable "i" output//help-this need help figuring out how stream output, 32_data, onto pin en_q <= ~en_q; // toggle en_q next 32bit stream "q" else if (en_q ==1) (stream 32bit info variable "q" onto pin 3) //variable "q" output//help-this need help figuring out how stream output, 32_data, onto pin en_q <= ~en_q; // toggle en_q next 32bit stream "i" end

if help me figuring out how stream 32 bit info stream onto pin, great! in advance

i have added suggestion. set info on pins loop? next code segment , bottom part shift register , outputting pin:

`// wires , registers related info capturing wire capture_clk; reg [31:0] capture_data; wire capture_en; reg [4:0] slowdown; wire capture_full;

reg capture_open; reg capture_open_cross; reg capture_has_been_full; reg capture_has_been_nonfull; reg has_been_full_cross; reg has_been_full; // info capture section // ==================== @(posedge capture_clk) begin if (capture_en) capture_data <= user_w_write_32_data; // bogus info source // slowdown register limits info pace 1/32 bus_clk // when capture_clk = bus_clk. necessary, because // core in evaluation kit configured simplicity, , // not performance. sustained info rates of 200 mb/sec // reached performance-oriented setting. // slowdown register has no function in real-life application. slowdown <= slowdown + 1; // capture_has_been_full remembers fifo has been total // until file closed. capture_has_been_nonfull prevents // capture_has_been_full respond initial total status // every fifo displays on reset. if (!capture_full) capture_has_been_nonfull <= 1; else if (!capture_open) capture_has_been_nonfull <= 0; if (capture_full && capture_has_been_nonfull) capture_has_been_full <= 1; else if (!capture_open) capture_has_been_full <= 0; end // dependency on slowdown bogus info assign capture_en = capture_open && !capture_full && !capture_has_been_full && (slowdown == 0); // clock crossing logic: bus_clk -> capture_clk @(posedge capture_clk) begin capture_open_cross <= user_r_read_32_open; capture_open <= capture_open_cross; end // clock crossing logic: capture_clk -> bus_clk @(posedge bus_clk) begin has_been_full_cross <= capture_has_been_full; has_been_full <= has_been_full_cross; end // user_r_read_32_eof signal required go '0' '1' on // clock cycle next asserted read enable, according xillybus' // core api. assured, since it's logical , between // user_r_read_32_empty , has_been_full. has_been_full goes high when // fifo full, it's guaranteed user_r_read_32_empty low when // happens. on other hand, user_r_read_32_empty fifo's empty // signal, naturally meets requirement. assign user_r_read_32_eof = user_r_read_32_empty && has_been_full; assign user_w_write_32_full = 0; // info capture clock here bus_clk simplicity, clock domain // crossing done properly, capture_clk can independent clock // without other changes. assign capture_clk = bus_clk; async_fifo_32x512 fifo_32 //fifo created using xilinx fifo generator wizard ( .rst(!user_r_read_32_open), .wr_clk(capture_clk), .rd_clk(bus_clk), .din(capture_data), .wr_en(capture_en), .rd_en(user_r_read_32_rden), .dout(user_r_read_32_data), .full(capture_full), .empty(user_r_read_32_empty) ); reg q_en = 1'b0; //starting value 0 because first 32bit reg [31:0] data_outi; reg [31:0] data_outq; reg i; reg q; integer counter; @(posedge bus_clk) begin if(q_en == 1'b0) begin //to output signal data_outi <= user_r_read_32_data; (counter = 0; counter < 32; counter = counter + 1) begin //output pins = data_outi[0]; data_outi <= (data_outi >> 1); q = data_outq[0]; data_outq <= (data_outq >> 1); end q_en <= ~q_en; end else if(q_en == 1'b1) begin //to output q signal data_outq <= user_r_read_32_data; (counter = 0; counter < 32; counter = counter + 1) begin //output pins = data_outi[0]; data_outi <= (data_outi >> 1); q = data_outq[0]; data_outq <= (data_outq >> 1); end q_en <= ~q_en; end end assign ps_gpio_one_i = i; //assign pin assign ps_gpio_two_q = q; //assign pin q

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basically, you'd want following:

fetch item fifo 32 bit register (lets phone call data) each clock cycle, set lsb of data onto pin, , right shift data 1 value. keep repeating shifting 32 clock cycles, until of info has been shifted out. toggle value of en_q, , fetch 32 bit item.

you should able create little state machine can handle sequence. can't shift out 32 bits in single clock cycle have done in pseudo-code, unless have 32x clock available, , more complicated design.

output verilog fifo bitstream