system verilog - do_compare has a result of 1 however .compare return value is 0 -



system verilog - do_compare has a result of 1 however .compare return value is 0 -

i'm next http://cluelogic.com/2013/01/uvm-tutorial-for-candy-lovers-do-hooks/ , https://verificationacademy.com/cookbook/transaction/methods implement compare difference instead of big logical , (&&) i'm using

virtual function bit do_compare .... do_compare &= <statement a>; do_compare &= <statement b>; $display (do_compare); ///< displays 1 homecoming do_compare; endfunction

however returned value comes out 0 e.g. consider sequences

temp = m.compare(n); $display (temp); ///< displays 0

i've been trying debug why temp 0 couldn't figure out. can point me in right direction

having in source code compare(...) see next status do_compare(...) called:

if(!done) begin comparer.compare_map.set(rhs, this); __m_uvm_field_automation(rhs, uvm_compare, ""); dc = do_compare(rhs, comparer); end

not sure when set done (one case when error flagged fields automated field macros). sure do_compare(...) beingness called? add together `uvm_info in there or set break point create sure.

another thought saw in presentation john aynsley not utilize field automation macros if want implement own do_* methods. in case using them, seek setting fields uvm_nocompare. because homecoming value of compare(...) computed return (comparer.result == 0 && dc == 1);. means if do_compare(...) returns 1, may still case 1 of automated fields flagged error (although have expected error message).

system-verilog uvm

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